High yield and process uniformity for 300 mm integrated WS 2 FETs

Abstract

We demonstrate an integrated process flow on full 300mm wafers with monolayer WS 2 channel. WS 2 is a 2D semiconductor from the transition metal dichalcogenide family and holds promise for extreme gate length scaling. We report here on integration challenges and optimize process uniformity for a single-device yield higher than 90% across wafer. These transistors and integration flow are shown to be compatible with H 2 anneal of at least 400 C and hence in principle suitable for hybrid integration in the BEOL.