//www.w3.org/1999/xlink">x dipole improves device performance and brings the BTI reliability within specification at low temperature.22:T4e7,3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, top junctionless (JL) devices are fabricated with a maximum processing temperature of 525 °C. The devices feature high k/metal replacement gate and low-temperature Si:P and SiGe:B 60% raised source and drain for nMOS and pMOS fabrication, respectively. Device matching, analog, and RF performance of the top tier devices are in-line with the state-of-the-art Si technology processed at high temperature (>1000 °C). JL devices operate at reduced electric field and can meet in specification reliability (10-year reliable operation at V _G = V _th + 0.6 V, 125 °C), even without the use of “reliability” anneal. The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding. Comparison with silicon-on-insulator devices fabricated with the same low-temperature flow shows no impact on device electrical performance from the Si layer transfer.23:T408,Integration of 2D-materials brings a new set of challenges to a 300 mm Si CMOS fab. We have opted for double gated WS 2 transistors as test vehicle with transition metal dichalcogenides as channel. Moreover, we explore two different routes within a modified industry standard flow, differentiating in channel deposition method either by direct deposition or via layer transfer. The integration flow mitigates the constraints of high surface sensitivity and low adhesion for these materials. Device performance of I on /I off up to 10 ⁷ is achieved and WIW mapping is obtained opening the route for further process understanding.

#	Concept	H-Index	Publications	Citations
1	Engineering	7	7	165
2	Applied Physics	7	7	165
3	Electrical Engineering	6	6	151
4	Computer Engineering	4	4	100
5	Materials Science	2	2	41

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