W. Li

Wafer-scale integration of double gated WS₂-transistors in 300mm Si CMOS fab

Inge Asselberghs, Quentin Smets, T. Schram et al. · 2020 · 55 citations

Engineering, Electrical Engineering, Materials Science +17

Vertical Nanowire and Nanosheet FETs: Device Features, Novel Schemes for Improved Process Control and Enhanced Mobility, Potential for Faster & More Energy Efficient Circuits

A. Veloso, Geert Eneman, Trong Huynh-Bao et al. · 2019 · 40 citations

Engineering, Electrical Engineering, Materials Science +17

First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers

A. Vandooren, J. Franco, Zhicheng Wu et al. · 2018 · 30 citations

Engineering, Electrical Engineering, Materials Science +17

3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability

A. Vandooren, J. Franco, Bertrand Parvais et al. · 2018 · 25 citations

Engineering, Electrical Engineering, Microelectronics +16

Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections

A. Vandooren, Narendra Parihar, J. Franco et al. · 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 2022 · 20 citations

Engineering, Computer Engineering, Electrical Engineering +17