IEEE Transactions on Electron Devices · 2021 · 52 citations · 38 references
EngineeringThin Film Process TechnologyHigh PerformanceSemiconductor DeviceSemiconductorsNanoelectronicsCompound SemiconductorHall EffectThin Film ProcessingMaterials ScienceSemiconductor TechnologyElectrical EngineeringOxide ElectronicsSemiconductor MaterialIgzo TftsMicroelectronicsElectronic MaterialsLow Subthreshold SwingApplied PhysicsThin FilmsIgzo Thin Films
Amorphous indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) were fabricated by plasma-enhanced atomic layer deposition (PEALD). The thicknesses of the IGZO thin films varied between 3 and 7.5 nm. The device parameters were optimized at 5 nm, at threshold voltage of -0.07 V, effective mobility of 34.16 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs, and subthreshold slope of 75 mV/decade and did not further improve with increasing thickness. To understand the origin of the saturated device properties, the accumulation thickness of TFTs was measured and calculated to be 6.4 nm. In addition, to investigate the origin of degraded properties of 3 nm IGZO TFTs, the Hall effect, interface trap density (D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> ), and series resistance were measured. The carrier concentrations were nearly constant regardless of the channel thickness, but the resistivity and Hall mobility were degraded considerably in the 3 nm IGZO. In addition, the D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> and series resistance in the 3 nm TFT were 1.49 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> /eVcm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 143.9 Ω cm, respectively, which are relatively higher than those of the other TFTs. Finally, the device reliability of IGZO TFTs under bias thermal stress was assessed. The threshold voltage shift was less than 1 V under 125 °C and 1.5 MV/cm stress conditions.
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FinFET scaling to 10 nm gate length
Bin Yu, Leland Chang, Safayet Ahmed et al. · 2003 · 592 citations