How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on

A low-voltage triggering SCR for on-chip ESD protection at output and input pads

Amitava Chatterjee, T. Polgreen · IEEE Electron Device Letters · 1991 · 243 citations

Engineering, Electrical Engineering, Microelectronics +13

Sub-micron chip ESD protection schemes which avoid avalanching junctions

E. Worley, Ratnesh Gupta, B.E. Jones et al. · 1995 · 110 citations

Engineering, Electrical Engineering, Microelectronics +9

Internal chip ESD phenomena beyond the protection circuit

C. Duvvury, R.N. Rountree, Oliver Adams · IEEE Transactions on Electron Devices · 1988 · 75 citations

Engineering, Electrical Engineering, Circuit Theory +8

A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS ICs

Ming‐Dou Ker, Hun-Hsien Chang, Chung‐Yu Wu · IEEE Journal of Solid-State Circuits · 1997 · 75 citations

Engineering, Computer Engineering, Electrical Engineering +14

Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI

Ming-Dou Ker, Chung‐Yu Wu, Hun-Hsien Chang · IEEE Transactions on Electron Devices · 1996 · 67 citations

Engineering, Electrical Engineering, Circuit Theory +9