2019 · 29 citations · 30 references
EngineeringComputer EngineeringComputer ScienceLow-power DesignParallel ComputingSystem-on-chip DesignDynamic Power ReductionPower ManagementPower OptimizationPower-aware DesignProcessor Core DesignVoltage ScalingCore Power ManagementDynamic Voltage And Frequency ScalingEnergy ConsumptionEnergy-efficient ArchitecturePower ConsumptionPower Consumption OptimizationPower Management TechniquesPower-aware Microarchitecture
Dynamic voltage and frequency scaling reduces power, but most processors only support chip‑level DVFS, whereas per‑core DVFS—available only on Haswell—offers finer control that can improve energy efficiency for unsynchronized parallel workloads and enables new runtime optimizations. The authors develop an intelligent runtime module that applies fine‑grained, function‑level per‑core DVFS to achieve energy efficiency. The module determines the energy‑optimal frequency for each phase, function, or kernel during the first few iterations and then applies that frequency to subsequent executions. On Haswell processors, the approach delivers 4 % to 35 % energy savings compared with chip‑level DVFS while maintaining comparable performance.
Dynamic voltage and frequency scaling (DVFS) is a well-known technique to reduce the power and/or energy consumption of various applications. While most processors provide chip-level DVFS, where the frequency and voltage of the cores in a chip can only be changed all together; core-level DVFS, where each core can be controlled independently, requires core-level voltage regulators in hardware and only is supported in production in Haswell generation among Intel processors. The finer grained control that per-core DVFS provides can lead to higher energy efficiency compared to chip-level DVFS especially for the unsynchronized, unstructured parallel applications when carefully applied. Ability to do per-core DVFS opens up new doors for different optimizations within runtime systems. We implement an intelligent energy efficient runtime module which uses a fine-grained function level per-core DVFS approach. Our module finds the energy-optimal frequency for each phase/function/kernel of the application over the first few iterations and applies the optimal frequency for each function. We test our implementation on Haswell processors and show that our algorithm enables 4% to 35% energy reduction over chip-level DVFS with as much as performance.
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Parameter variations and impact on circuits and microarchitecture
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Engineering, Computer Engineering, Computer Architecture +15