Power Reduction and BTI Mitigation of Data-Cache Memory Based on the Storage Management of Narrow-Width Values

Abstract

Power dissipation of on-chip cache memories contributes a large portion of a processor's power consumption. Therefore, power management of cache memories is crucial in modern processors. On the other hand, bias temperature instability (BTI) is one of the most serious reliability concerns in SRAM-based on-chip memories. The effect of BTI on SRAM-cell transistors is manifested as their threshold-voltage shift over stress duration, which decreases the robustness of these structures. This paper presents a power consumption-reduction technique for data-cache memories, based on a storage management considering narrow-width values (NWVs), which additionally mitigates the BTI rate on the most aging susceptible SRAM cells of data-cache memory, as well. In the proposed technique, the most significant bits of data-cache memory words are stored in SRAM blocks that operate with lower V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> , to achieve the decrease of the related power consumption and aging rate. This is shown to reduce leakage-current and dynamic current of data-cache memory by 37.6% and 22.1%, respectively, besides improving its lifetime by up to 2.25x, all with negligible performance and area overheads.