The gem5 simulator

TLDR

gem5 merges M5’s configurable, multi‑ISA framework with GEMS’s detailed memory and coherence models, developed through a broad academic and industrial collaboration. It supports most commercial ISAs, boots Linux on ARM, ALPHA, and x86, has been cited in hundreds of papers and downloaded tens of thousands of times, and its collaborative development and BSD‑like license make it a valuable full‑system simulator.

Abstract

The gem5 simulation infrastructure is the merger of the best aspects of the M5 [4] and GEMS [9] simulators. M5 provides a highly configurable simulation framework, multiple ISAs, and diverse CPU models. GEMS complements these features with a detailed and exible memory system, including support for multiple cache coherence protocols and interconnect models. Currently, gem5 supports most commercial ISAs (ARM, ALPHA, MIPS, Power, SPARC, and x86), including booting Linux on three of them (ARM, ALPHA, and x86). The project is the result of the combined efforts of many academic and industrial institutions, including AMD, ARM, HP, MIPS, Princeton, MIT, and the Universities of Michigan, Texas, and Wisconsin. Over the past ten years, M5 and GEMS have been used in hundreds of publications and have been downloaded tens of thousands of times. The high level of collaboration on the gem5 project, combined with the previous success of the component parts and a liberal BSD-like license, make gem5 a valuable full-system simulation tool.