StrongARM Latch Comparator Performance Enhancement by Implementing Clocked Forward Body Biasing

Abstract

In this paper, we propose a forward body biasing technique to enhance the performance of the StrongARM comparators. We apply this technique, which is mainly based on clocked tuning of the threshold voltage of the NMOS cross-coupled transistors, to different architectures, namely: Kobayashi, Razavi, and Improved StrongARM comparators. The circuits are simulated in the standard 65nm CMOS technology and performance improvement of up to 20.8% has been achieved while maintaining the same energy loss.