IEEE Micro · 2019 · 19 citations · 14 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureLow-power DesignMemoryMemory DevicesMemory HierarchyMemory Hierarchy DesignMemory Hierarchy OptimizationMemory Subsystem DesignMemristive MaterialsData-intensive ComputingEnergy-efficient Memory DesignMemory Controller DesignMemristive MemoryNon-volatile Memory DesignResistive Random-access MemoryScalabilityVon Neumann Architecture
While DRAM cannot easily scale below a 20-nm technology node, RRAM suffers far less from scalability issues. Moreover, RRAM's resistivity enables its use for processing-in-memory (PIM), potentially alleviating the von Neumann bottleneck. Unfortunately, because of technological idiosyncrasies, existing DRAM-centric memory controllers cannot exploit the full potential of resistive RAM (RRAM). In this paper, we present the design of a memory controller called CONCEPT. The controller is optimized to exploit unique properties of RRAM to enhance its performance and energy efficiency as well as exploiting RRAM's PIM capability. We show that with CONCEPT, RRAM can achieve DRAM-like performance and energy efficiency on SPEC CPU 2006 benchmarks. Furthermore, using RRAM PIM capabilities, we show a 5× performance gain on a data-intensive in-memory database workload compared to a state-of-the-art CPU-memory computing model.
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Shahar Kvatinsky, Slavik Liman, Guy Satat et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 2014 · 824 citations
Engineering, Computer Engineering, Electrical Engineering +14
Shuangchen Li, Cong Xu, Qiaosha Zou et al. · 2016 · 432 citations
Vivek Seshadri, Donghyuk Lee, Thomas Mullins et al. · 2017 · 428 citations