2017 · 428 citations · 94 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureParallel ComputingReconfigurable ComputingData ParallelismHardware AccelerationMemory Hierarchy OptimizationParallel ArchitecturesParallel Computing SystemsReconfigurable AcceleratorsAccelerator MicroarchitectureBit VectorsBitmap IndexingBitwise OperationsData-intensive ComputingMemory BandwidthProcessingWeb Search Architecture
Many important applications trigger bulk bitwise operations, i.e., bitwise operations on large bit vectors. In fact, recent works design techniques that exploit fast bulk bitwise operations to accelerate databases (bitmap indices, BitWeaving) and web search (BitFunnel). Unfortunately, in existing architectures, the throughput of bulk bitwise operations is limited by the memory bandwidth available to the processing unit (e.g., CPU, GPU, FPGA, processing-in-memory).
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Fast and accurate short read alignment with Burrows–Wheeler transform
Heng Li, Richard Durbin · Bioinformatics · 2009 · 62.8K citations · Full text
Fast and accurate long-read alignment with Burrows–Wheeler transform
Heng Li, Richard Durbin · Bioinformatics · 2010 · 12.9K citations · Full text
Space/time trade-offs in hash coding with allowable errors
Burton H. Bloom · Communications of the ACM · 1970 · 7.5K citations · Full text
Error Detecting and Error Correcting Codes
R. W. Hamming · Bell System Technical Journal · 1950 · 5.1K citations · Full text
Nathan Binkert, Bradford M. Beckmann, Gabriel Black et al. · ACM SIGARCH Computer Architecture News · 2011 · 4.9K citations