NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory

TLDR

Recent advances have produced several promising nonvolatile memory technologies—STT‑RAM, PCRAM, and ReRAM—but design tools for these devices are lacking. This work develops NVSim, a circuit‑level model that estimates performance, energy, and area for NVM technologies to support design space exploration across memory hierarchy levels. NVSim implements a circuit‑level model that estimates performance, energy, and area for multiple NVM technologies, including STT‑RAM, PCRAM, ReRAM, and legacy NAND Flash. NVSim was validated against industrial prototypes and is expected to accelerate architecture‑level NVM research.

Abstract

Various new nonvolatile memory (NVM) technologies have emerged recently. Among all the investigated new NVM candidate technologies, spin-torque-transfer memory (STT-RAM, or MRAM), phase-change random-access memory (PCRAM), and resistive random-access memory (ReRAM) are regarded as the most promising candidates. As the ultimate goal of this NVM research is to deploy them into multiple levels in the memory hierarchy, it is necessary to explore the wide NVM design space and find the proper implementation at different memory hierarchy levels from highly latency-optimized caches to highly density- optimized secondary storage. While abundant tools are available as SRAM/DRAM design assistants, similar tools for NVM designs are currently missing. Thus, in this paper, we develop NVSim, a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash. NVSim is successfully validated against industrial NVM prototypes, and it is expected to help boost architecture-level NVM-related studies.