Pinatubo

TLDR

Processing‑in‑memory (PIM) offers high bandwidth, massive parallelism, and energy efficiency by performing computations directly in main memory, thereby eliminating data‑movement overhead between CPU and memory. The authors propose leveraging non‑volatile memory (NVM) features to enable efficient PIM design, introducing the Pinatubo architecture for bulk bitwise operations. Pinatubo redesigns the read circuitry to compute bitwise logic across multiple memory rows in a single step, enabling efficient bulk bitwise operations without complex logic inside the memory. Experiments on graph‑processing and database workloads show Pinatubo delivers about 500× speedup and 28,000× energy savings on bitwise operations, and 1.12× overall speedup and 1.11× overall energy savings versus a conventional processor.

Abstract

Processing-in-memory (PIM) provides high bandwidth, massive parallelism, and high energy efficiency by implementing computations in main memory, therefore eliminating the overhead of data movement between CPU and memory. While most of the recent work focused on PIM in DRAM memory with 3D die-stacking technology, we propose to leverage the unique features of emerging non-volatile memory (NVM), such as resistance-based storage and current sensing, to enable efficient PIM design in NVM. We propose Pinatubo1, a <u>P</u>rocessing <u>I</u>n <u>N</u>on-volatile memory <u>A</u>rchi<u>T</u>ecture for b<u>U</u>lk <u>B</u>itwise <u>O</u>perations. Instead of integrating complex logic inside the cost-sensitive memory, Pinatubo redesigns the read circuitry so that it can compute the bitwise logic of two or more memory rows very efficiently, and support one-step multi-row operations. The experimental results on data intensive graph processing and database applications show that Pinatubo achieves a ~500× speedup, ~28000× energy saving on bitwise operations, and 1.12× overall speedup, 1.11× overall energy saving over the conventional processor.