IEEE Transactions on Components Packaging and Manufacturing Technology · 2018 · 46 citations · 38 references
EngineeringElectrical EngineeringMaterials EngineeringMicroelectromechanical SystemsMicrofabricationSemiconductor DevicesChip PackagingIntegrated Circuit DesignIntegrated Circuit DevicesIntegrated Circuit FabricationInterconnect TechnologyWafer BondingDie-to-wafer BondingFan-out Wafer-level PackagingFlexible ElectronicsFlexible SubstratesHeterogeneous Device IntegrationHeterogeneous IntegrationSilicon Wafer ProcessingWafer-level Packaging
A technological platform is established for scalable flexible hybrid electronics based on a novel fan-out wafer-level packaging (FOWLP) methodology. Small dielets are embedded in flexible substrates we call FlexTrate. These dielets can be interconnected through high-density wirings formed in wafer-level processing. We demonstrate homogeneous integration of 625 (25 by 25) 1-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> Si dielets and heterogeneous integration of GaAs and Si dielets with various thicknesses in a biocompatible polydimethylsiloxane (PDMS). In this paper, 8-μm-pitch die-todie interconnections are successfully implemented over a stress buffer layer formed on the PDMS. In addition, coplanarity between the PDMS and embedded dielets, die shift concerned in typical die-first FOWLP, and the bendability of the resulting FlexTrate are characterized.
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