Cost Effective FinFET Platform for Stand Alone DRAM 1Y and Beyond Memory Periphery

Abstract

A new platform for Memory periphery device based on FinFET technology is proposed, targeting DRAM technology node 1Y and beyond. Up to 30% power saving is demonstrated at system level with respect to a conventional planar SiON based solution, thanks to an optimized cost-effective process flow (~38% less expensive than equivalent logic flow), compatible with a DRAM technology. This makes the solution perfectly suitable for low power mobile applications or enabling faster server applications. The additional sensing margin can be used to aggressively reduce the analog area (>50%) or to mitigate the process concern on the memory array, paving the way for the introduction of different storage elements. An overview of the device characteristics based on the fabricated hardware is presented, exploring potential knobs to further improve the transistors.