Effect of air spacer on analog performance of underlap tri-gate FinFET

Analysis of the Parasitic S/D Resistance in Multiple-Gate FETs

Abhisek Dixit, Anil Kottantharayil, Nadine Collaert et al. · IEEE Transactions on Electron Devices · 2005 · 355 citations

Engineering, Electrical Engineering, Electronic Materials +16

Nanoscale FinFETs with gate-source/drain underlap

Vishal Trivedi, J.G. Fossum, M.M. Chowdhury · IEEE Transactions on Electron Devices · 2004 · 272 citations

Engineering, Electrical Engineering, Electronic Materials +16

Extension and source/drain design for high-performance finFET devices

J. Kedzierski, M. Ieong, E. Nowak et al. · IEEE Transactions on Electron Devices · 2003 · 244 citations

Engineering, Electrical Engineering, Electronic Materials +16

Design and Optimization of FinFETs for Ultra-Low-Voltage Analog Applications

Abhinav Kranti, G.A. Armstrong · IEEE Transactions on Electron Devices · 2007 · 108 citations

Engineering, Electrical Engineering, Analog Electronics +10

Modeling and Significance of Fringe Capacitance in Nonclassical CMOS Devices With Gate–Source/Drain Underlap

S.-H. Kim, J.G. Fossum, Ji‐Woon Yang · IEEE Transactions on Electron Devices · 2006 · 94 citations

Engineering, Electrical Engineering, Microelectronics +16