3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance

Abstract

This paper describes logic and circuit design features of a heterogeneous tri-cluster deca-core CPU complex incorporated into a 10nm FinFET mobile SoC for smartphone applications. Similar to Helio X20 [1], the Deca-Core compute function contains three separate clusters of ARMv8a CPUs. The high-performance (HP) cluster is updated to incorporate the most power-efficient out-of-order Cortex-A73 CPU, operating at max frequency of 2.8GHz. In X20, the low-power (LP) and ultra-low power (ULP) clusters used Cortex-CA53 with different implementation flows, while this work achieves a +44% more power-efficient ULP solution based on the newer Cortex-CA35 CPU (Fig. 3.4.1). In addition, the LP cluster achieves a +36% more performance than ULP or +40% more power-efficiency than the HP cluster, for optimal sustainable performance/power applications including augmented reality and virtual reality (AR/VR). A die photograph, Fig. 3.4.7, highlights the three CPU clusters.