Gordon Gammie - Concepedia

Author

Gordon Gammie

Texas Instruments (United States)

Also Known As

G Gammie, G. Gammie, Gordon Gammie

Publications

478

Citations

H-Index

Concepts

All Affiliations

Texas Instruments (United States)Massachusetts Institute of Technology MediaTek (Taiwan)MediaTek (China)MaxLinear (United States)

About

Gordon Gammie is an author at Texas Instruments (United States) specializing in engineering, computer engineering, and computer architecture.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	12	13	421
2	Computer Engineering	12	12	410
3	Computer Science	2	2	46
4	Education	1	1	20
5	Applied Physics	1	1	11

Gordon Gammie

Publications

431

Citations

H-Index

Page 1

	Year	Citations
A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques Gordon Gammie, Alice Wang, Minh Quang Chau, EngineeringRadio FrequencyMultimedia ProcessorComputer ArchitectureProcessor Architecture	2008	71
A 65-nm Mobile Multimedia Applications Processor with an Adaptive Power Management Scheme to Compensate for Variations H. Mair, A. Wang, Gordon Gammie, EngineeringEnergy EfficiencyAdaptive CompensationMultimedia ProcessorComputer Architecture	2007	65
A 28 nm 0.6 V Low Power DSP for Mobile Applications Nathan Ickes, Gordon Gammie, Mahmut E. Sinangil, IEEE Journal of Solid-State Circuits EngineeringVlsi DesignLocal Transistor ThresholdComputer ArchitectureUltra-low Voltage Operation	2011	58
SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors Gordon Gammie, A. Wang, H. Mair, Proceedings of the IEEE EngineeringEnergy EfficiencyPower Optimization (Eda)Smartreflex PowerComputer Architecture	2010	36
A 28nm 0.6V low-power DSP for mobile applications Gordon Gammie, Nathan Ickes, Mahmut E. Sinangil, Low-power ElectronicsHardware SecurityElectrical EngineeringL2 CachesEngineering	2011	29
4.3 A 20nm 2.5GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance H. Mair, Gordon Gammie, Alice Wang, Deca-core Cpu SubsystemEngineeringVlsi DesignPower Optimization (Eda)Computer Architecture	2016	27
The Effect of Random Dopant Fluctuations on Logic Timing at Low Voltage Rahul Rithe, Sharon H. Chou, Jie Gu, IEEE Transactions on Very Large Scale Integration (VLSI) Systems Low-power ElectronicsRandom Dopant FluctuationsElectrical EngineeringLogic TimingEngineering	2011	26
3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance Hugh Mair, Lin Gordon, Achuta Thippana, Finfet 2.8GhzEngineeringVlsi DesignComputer ArchitectureCircuit Design Features	2017	26
23.3 A highly integrated smartphone SoC featuring a 2.5GHz octa-core CPU with advanced high-performance and low-power techniques Hugh Mair, Gordon Gammie, Alice Wang, Integrated Mobile SocVlsi DesignEngineeringComputer ArchitectureIntegrated Circuits	2015	23
10.3 heterogeneous multi-processing quad-core CPU and dual-GPU design for optimal performance, power, and thermal tradeoffs in a 28nm mobile application processor Alice Wang, Tsung-Yao Lin, Shichin Ouyang, Heterogeneous ComputingEngineeringEnergy EfficiencyMobile DevicesComputer Architecture	2014	20

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