A 28nm 0.6V low-power DSP for mobile applications

Abstract

A multimedia applications processor is fabricated using a 28nm low-power process technology for ultra-low-power applications. Based on a 4-issue, 32 register version of the TMS320C64X+ VLIW DSP, this System on Chip (SoC) includes 32kB L1 and 128kB L2 caches, and I2S, SPI, UART, MultiMediaCard, and external memory interfaces (Fig. 7.5.1). The design incorporates over 600k instances of custom low-voltage logic cells and 43 instances (1.6 Mb) of 6T SRAM. Utilizing ultra-low-voltage (ULV) optimized standard-cell libraries and 6T SRAM macros, and demonstrating a new statistical static timing analysis (SSTA) methodology, the SoC scales as designed from high performance at 1.0V down to ultra-low power at 0.6V.