Considerations for Static Energy Reduction in Digital CMOS ICs Using NEMS Power Gating

Abstract

Due to its infinite OFF resistance, Nano-Electro-Mechanical Switches (NEMS) have been recently proposed to reduce leakage current during the standby mode in large-scale Digital ICs in nano regime area. However, detailed analysis of the conditions at which the NEMS devices will have impact is missing. In this brief, the technique of power gating is analyzed with a NEMS switch using detailed circuit level simulations to obtain the conditions under which one can obtain net energy savings as compared with FinFET-based power gating. Finally, applicability in the energy reduction on a futuristic system-on-chip for mobile platform made using 14 nm gate length FinFET device is evaluated.