A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications

Abstract

In low voltage SRAM for IoT application, although static noise margin (SNM) and write margin (WM) decide VMIN, Icell / Ioff ratio and Icell are also important in order to keep performance and achieve better operating efficiency. We propose a new mixed Vth RP design which can achieve better Icell and Icell / Ioff ratio. Furthermore, combination of the proposed mixed Vth and boosted read wordline (RWL) scheme improves the worst case bitline delay time by 72.3% at 0.45V. In the measurement results, we confirmed a minimum operating voltage (VMIN) for the 64 Kb SRAM of 0.370 V with 99% yield at room temperature.