Worst-case Delay Estimation

Worst-Case Delay Estimation is a timing analysis method that determines the maximum possible propagation delay of a signal path in a digital circuit under all feasible process, voltage, temperature, and crosstalk variations to ensure reliability in timing-critical designs.

200

Publications

8.2K

Citations

432

Authors

161

Institutions

Publications per year

2017–2026

16

Authors

432

  1. CF
    Christian Fraboul

    Institut National Polytechnique de Toulouse, France

    8 publications · 338 citations

    8

    h-index

  2. DB
    David Blaauw

    University of Michigan, United States

    8 publications · 336 citations

    8

    h-index

  3. YX
    Yuan Xie

    Pennsylvania State University, United States

    6 publications · 107 citations

    6

    h-index

  4. FN
    Farid N. Najm

    University of Toronto, Canada

    6 publications · 216 citations

    6

    h-index

  5. LT
    Lothar Thiele

    ETH Zurich, Switzerland

    6 publications · 394 citations

    6

    h-index

1–5 of 432

Venues

  1. 14

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  2. 4

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  3. ACM Transactions on Design Automation of Electronic Systems

    TODAES · 3 publications · 55 citations

    3

    h-index

  4. 3

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  5. 3

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1–5