Worst-case Delay Estimation
Worst-Case Delay Estimation is a timing analysis method that determines the maximum possible propagation delay of a signal path in a digital circuit under all feasible process, voltage, temperature, and crosstalk variations to ensure reliability in timing-critical designs.
200
Publications
8.2K
Citations
432
Authors
161
Institutions
Publications per year
2017–2026
16
Parents
200
Path sensitization in critical path problem
H.-C. Chen, David H. C. Du · 2002 · 224 citations
Speeding up processing with approximation circuits
Shih‐Lien Lu · Computer · 2004 · 223 citations
Bounding memory interference delay in COTS-based multi-core systems
Hyoseung Kim, Dionisio de Niz, Björn Andersson et al. · 2014 · 209 citations · Full text
Support of voice services in IEEE 802.11 wireless LANs
Malathi Veeraraghavan, N. Cocker, Tim Moors · 2002 · 207 citations
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161
University of Southern California
Los Angeles, United States
10 h-index
46 publications
1.5K citations
University of Illinois Urbana-Champaign
Urbana, United States
9 h-index
18 publications
934 citations
University of California, Santa Barbara
Santa Barbara, United States
9 h-index
19 publications
695 citations

Université Fédérale de Toulouse Midi-Pyrénées
Toulouse, France
9 h-index
25 publications
1.1K citations

Université Toulouse III - Paul Sabatier
Toulouse, France
8 h-index
21 publications
983 citations
Institut National Polytechnique de Toulouse
Toulouse, France
8 h-index
19 publications
905 citations
Carnegie Mellon University
Pittsburgh, United States
8 h-index
22 publications
2.6K citations
Intel (United States)
Santa Clara, United States
8 h-index
20 publications
1.1K citations
1–8 of 161
15 publications · 768 citations
14
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4 publications · 287 citations
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TODAES · 3 publications · 55 citations
3
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3 publications · 229 citations
3
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Conference · 3 publications · 131 citations
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