Shih‐Lien Lu - Concepedia

Author

Shih‐Lien Lu

Intel (United States)

Also Known As

Lu, Lu, Shih-Lien, Shih-Lien Linus Lu, Shih-Lien Lu, Shih-lien Lu, Shih‐Lien Lu

116

Publications

3.2K

Citations

H-Index

Concepts

All Affiliations

Intel (United States)Oregon State University University of Maryland, College Park University of Florida Intel (United Kingdom)

About

Shih‐Lien Lu is an author at Intel (United States) specializing in computer engineering, engineering, and computer architecture.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	27	40	2.9K
2	Computer Engineering	27	39	2.8K
3	Computer Science	20	27	2.2K
4	Management	3	3	142
5	Applied Physics	2	2	59

Shih‐Lien Lu

Publications

Citations

H-Index

Page 1

	Year	Citations
Trading off Cache Capacity for Reliability to Enable Low Voltage Operation Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, EngineeringVlsi DesignEnergy EfficiencyComputer ArchitectureLow Voltage Operation	2008	243
Speeding up processing with approximation circuits Shih‐Lien Lu Computer EngineeringVlsi DesignComputer ArchitectureComputational ComplexityHardware Security	2004	222
Reducing cache power with low-cost, multi-bit error-correcting codes Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Hardware SecurityNon-volatile MemoryElectrical EngineeringEngineeringError Control Technique	2010	198
RAMP: Research Accelerator for Multiple Processors John Wawrzynek, David A. Patterson, Mark Oskin, IEEE Micro EngineeringComputer ArchitectureResearch AcceleratorSoftware EngineeringHardware Architecture	2007	170
Technology comparison for large last-level caches (L<sup>3</sup>Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM Mu-Tien Chang, Paul Rosenfeld, Shih‐Lien Lu, EngineeringMemory DesignEmerging Memory TechnologyComputer ArchitectureLow Density	2013	170
Improving cache lifetime reliability at ultra-low voltages Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Hardware SecurityLow-power ElectronicsElectrical EngineeringReliability EngineeringPower-aware Computing	2009	167
Energy-efficient cache design using variable-strength error-correcting codes Alaa R. Alameldeen, Ilya Wagner, Zeshan Chishti, EngineeringVlsi DesignError Control TechniqueEnergy EfficiencyComputer Architecture	2011	146
Coming challenges in microarchitecture and architecture Ronny Ronen, Avi Mendelson, K. Lai, Proceedings of the IEEE Microprocessor DesignEngineeringVlsi DesignComputer ArchitectureProcessor Architecture	2001	142
DRAM Refresh Mechanisms, Penalties, and Trade-Offs Ishwar Bhati, Mu-Tien Chang, Zeshan Chishti, IEEE Transactions on Computers Hardware SecurityNon-volatile MemoryData Retention TimeEngineeringDram Refresh Mechanisms	2015	141
Circuit techniques for dynamic variation tolerance Keith Bowman, James Tschanz, Chris Wilkerson, Hardware SecurityElectrical EngineeringEngineeringVlsi DesignCircuit Design	2009	127

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