A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS

Abstract

The paper presents an SRAM array with bit interleaving and read scheme. The SRAM test-chip is fabricated in a 90nm CMOS technology. For leakage comparison, 49 kb arrays are implemented for both the conventional 6T cell and 10T cell. The leakage power consumption of this SRAM is close to that of the 6T cell (between 0.96times and 1.1times) even though it has extra transistors in a cell. This is because the subthreshold leakage from the bitline to the cell node is drastically reduced by the stacking of devices in the leakage path. The design operates at 31.25 kHz with a 0.18 V supply. With more aggressive wordline boosting of 80 mV, the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> scales down to 0.16 V at 0.16 V V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> , the operating frequency is 500 Hz and power consumption is 0.123 muW.