An n-well CMOS dynamic RAM

Abstract

A new n-well CMOS dynamic RAM is proposed. Experimental results with a 4K RAM, fabricated with advanced 2-µm lithography, are presented. For the design of RAM's greater than 256K, two major problems need to be solved: the increase in substrate current, and alpha-particle-induced soft errors. The new n-well CMOS RAM technology provides a solution to these problems. Use of PMOS transistors as load elements in peripheral circuits of the n-well CMOS RAM reduces the substrate current by at least two orders of magnitude. In addition, the potential barrier between the n-type, well and the p-type substrate rejects holes generated in the substrate, resulting in the reduction of soft error rates.