K. Shimohigashi - Concepedia

Author

K. Shimohigashi

Hitachi (Japan)

Also Known As

K. Shimohigashi, Katsuhiro Shimohigashi, T. Wada

Publications

1.4K

Citations

H-Index

Concepts

All Affiliations

Hitachi (Japan)Fairchild Semiconductor (United States)Stanford University Kyushu University

About

K. Shimohigashi is an author at Hitachi (Japan) specializing in engineering, electrical engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	20	28	1.1K
2	Computer Engineering	14	17	849
3	Applied Physics	10	10	239
4	Natural Sciences	3	3	62
5	Computer Science	1	1	30

K. Shimohigashi

Publications

1.2K

Citations

H-Index

Page 1

	Year	Citations
A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic Kazuo Yano, Toshiaki Yamanaka, Takashi Nishida, IEEE Journal of Solid-State Circuits Electrical EngineeringEngineeringVlsi DesignHigh-speed ElectronicsComplementary Pass-transistor Logic	1990	458
A 3.8 ns CMOS 16&amp;times;16 multiplier using complementary pass transistor logic Kazuo Yano, Toshiaki Yamanaka, Takashi Nishida,	1989	58
Short-channel MOSFET's in the punchthrough current mode J.J. Barnes, K. Shimohigashi, R.W. Dutton IEEE Transactions on Electron Devices Device ModelingSemiconductor TechnologyElectrical EngineeringEngineeringElectronic Engineering	1979	44
0.1 mu m CMOS devices using low-impurity-channel transistors (LICT) Masashi Aoki, Tatsuya Ishii, Teizo Yoshimura, Low-power ElectronicsElectrical EngineeringElectronic DevicesEngineeringVlsi Design	2002	44
Low-voltage ULSI design K. Shimohigashi, Kazuhiko Seki IEEE Journal of Solid-State Circuits Low-power ElectronicsHardware SecurityElectrical EngineeringElectronic DevicesElectronic Circuits	1993	43
An experimental large-capacity semiconductor file memory using 16-levels/cell storage Masashi Horiguchi, Masahiro Aoki, Y. Nakagome, IEEE Journal of Solid-State Circuits Non-volatile MemoryEngineeringMemory DesignEmerging Memory TechnologyComputer Architecture	1988	42
Design and performance of 0.1- mu m CMOS devices using low-impurity-channel transistors (LICT's) Masakazu Aoki, Tatsuya Ishii, Teizo Yoshimura, IEEE Electron Device Letters Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignNormal Transistor Operation	1992	41
A BiCMOS logic gate with positive feedback Yoshifumi Nishio, F. Murabayashi, S. Kotoku, Low-power ElectronicsElectrical EngineeringBicmos Process TechnologyQuantum ComputingHigh-speed Electronics	2003	35
A 16-level/cell dynamic memory Masahiro Aoki, Y. Nakagome, Masashi Horiguchi, IEEE Journal of Solid-State Circuits Storage LevelsElectrical EngineeringNon-volatile MemoryEngineering16-Level/cell Dynamic Memory	1987	30
Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register Y. Idei, K. Shimohigashi, Masakazu Aoki, IEEE Journal of Solid-State Circuits Non-volatile MemoryElectrical EngineeringDual-period Self-refresh SchemeEngineeringProm Register	1998	28

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