A 3.8 ns CMOS 16×16 multiplier using complementary pass transistor logic

Abstract

A 3.8-ns, 257-mW CMOS 16×16 multiplier with a supply voltage of 4 V is described. A complementary pass transistor logic (CPL) is proposed and applied to almost the entire critical path. The CPL consists of complementary input/output, an NMOS-pass-transistor logic network, and CMOS output inverters. The CPL is twice as fast as the conventional CMOS due to lower input capacitance and greater logic construction ability. Its multiplication time is believed to be the fastest ever reported, even including times of bipolar and GaAs ICs, and it is shown to be further enhanced to 2.6 ns and 60 mW at 77 K