0.5 micron CMOS for high performance at 3.3 V

Abstract

In addition to higher packing density, the scaling of CMOS technology to the half-micron regime must provide improved circuit performance at a reduced supply voltage without increased process complexity. These goals have been met with a 0.5- mu m CMOS technology with 12-nm gate oxide thickness that gives at least a 20% speed improvement at a 3.3-V supply voltage compared to an 0.8- mu m technology at 5.0 V with 20-nm gate oxide. Adequate process margin is obtained by requiring that transistors patterned 0.1 mu m shorter than design length fully meet the requirements for minimum short-channel leakage and sensitivity to hot-carrier stress.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>