Effects of Basal Plane Dislocation Density in 4H-SiC Substrate on Degradation of Body-Diode Forward Voltage

Abstract

We investigated the effect of the basal plane dislocation (BPD) density in 4H-silicon carbide (SiC) substrates on the forward voltage (V sd ) degradation of body-diodes. Using reflection X-ray topography, the BPD density was automatically estimated from the substrates prior to fabrication of metal–oxide–semiconductor field-effect transistors (MOSFETs). A strong positive correlation was found between the V sd shift, which was calculated from the difference before and after forward bias stress at 160 A/cm 2 for ~500 hours, and the BPD density of the substrate. We show that it is possible to predict V sd shifts from the BPD densities of SiC substrates prior to the fabrication of MOSFETs. In addition, we examined the origin of stacking faults (SFs) as a result of the application of forward bias stress. We presume that SFs are formed by BPDs converted to threading edge dislocations at the epi/sub interface, as well as by BPDs penetrating into the epitaxial layer.