3.7 A 40-to-64Gb/s NRZ transmitter with supply-regulated front-end in 16nm FinFET

Yohan Frans, Scott McLeod, Hiva Hedayati, Mohamed Elzeftawi, Jin Namkoong, Winson Lin, Jay Im, Parag Upadhyaya, Ken Chang

2016 · 14 citations · 4 references

Concepts

Abstract

Due to increasing bandwidth demand in data centers and telecommunication infrastructures, the maximum data-rate of wireline transceivers is projected to double from 32Gb/s to 64Gb/s while keeping the same power envelope. This paper presents the design of a 64Gb/s NRZ transmitter for short-reach electrical links in a 16nm FinFET process. It is applicable to standards such as CEI-56-VSR/MR, using power efficient techniques that take into considerations FinFET device properties: low DIBL, negligible body effect, low junction capacitance, low channel leakage, high intrinsic gain, high gate capacitance and resistance, high flicker noise, and steep CV curve in accumulation region.

References

4