Concepedia

Parag Upadhyaya

PU

Statistics

Publications

33

Citations

1.1K

H-Index

21

Active since

2004

Affiliations

Xilinx (United States)(Current)

Washington State University

Xilinx (Ireland)

University of California, Berkeley

National Taiwan University

Parag Upadhyaya is an author at Xilinx (United States) specializing in electrical engineering, engineering, and computer engineering.

Publications per year

2004–2024

33

Publications

33

A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET

Yohan Frans, Jaewook Shin, Lei Zhou et al. · IEEE Journal of Solid-State Circuits · 2017 · 162 citations

Engineering, Computer Engineering, Electrical Engineering +17

A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET

Parag Upadhyaya, Chi Fung Poon, Siok Wei Lim et al. · 2018 · 90 citations

Engineering, Computer Engineering, Electrical Engineering +14

A 7.4-to-14GHz PLL with 54fs<inf>rms</inf> jitter in 16nm FinFET for integrated RF-data-converter SoCs

Didem Turker, Ade Bekele, Parag Upadhyaya et al. · 2018 · 69 citations

Engineering, Electrical Engineering, Analog Electronics +16

A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET

Jay Im, Freitas Dave, Arianne Roldan et al. · IEEE Journal of Solid-State Circuits · 2017 · 60 citations

Engineering, Computer Engineering, Electrical Engineering +16

2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS

Jun‐Chau Chien, Parag Upadhyaya, Howard Jung et al. · 2014 · 52 citations

Engineering, Computer Engineering, Electrical Engineering +17

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