Parag Upadhyaya

A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET

Yohan Frans, Jaewook Shin, Lei Zhou et al. · IEEE Journal of Solid-State Circuits · 2017 · 155 citations

Further Equalization, Analog Equalization, Data Converter +6

A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET

Parag Upadhyaya, Chi Fung Poon, Siok Wei Lim et al. · 2018 · 90 citations

Low-power Electronics, Hardware Security, Electrical Engineering +11

A 7.4-to-14GHz PLL with 54fs<inf>rms</inf> jitter in 16nm FinFET for integrated RF-data-converter SoCs

Didem Turker, Ade Bekele, Parag Upadhyaya et al. · 2018 · 69 citations

Low-power Electronics, Electrical Engineering, Engineering +14

A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET

Jay Im, Freitas Dave, Arianne Roldan et al. · IEEE Journal of Solid-State Circuits · 2017 · 59 citations

Dfe Tap, Electrical Engineering, Engineering +8

2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS

Jun‐Chau Chien, Parag Upadhyaya, Howard Jung et al. · 2014 · 52 citations

Hardware Security, Engineering, Vlsi Design +12