Yohan Frans

A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET

Yohan Frans, Jaewook Shin, Lei Zhou et al. · IEEE Journal of Solid-State Circuits · 2017 · 155 citations

Further Equalization, Analog Equalization, Data Converter +6

A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET

Jay Im, Kevin Zheng, Chuen-Huei Adam Chou et al. · IEEE Journal of Solid-State Circuits · 2020 · 111 citations

7-Nm Finfet Cmos, Clock Recovery, Data Converter +6

A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET

Parag Upadhyaya, Chi Fung Poon, Siok Wei Lim et al. · 2018 · 90 citations

Low-power Electronics, Hardware Security, Electrical Engineering +11

A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling

Brian Leibowitz, R. Palmer, John W. Poulton et al. · IEEE Journal of Solid-State Circuits · 2010 · 84 citations

Hardware Security, Low-power Electronics, Electrical Engineering +15

6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET

Jay Im, Kevin Zheng, Adam Chou et al. · 2020 · 83 citations

Engineering, Vlsi Design, Clock Recovery +8