Yohan Frans - Concepedia

Author

Yohan Frans

Xilinx (United States)ORCID

Also Known As

Frans Yohan, Y. Frans, Yohan Frans

Publications

1.7K

Citations

H-Index

Concepts

All Affiliations

Xilinx (United States)Xilinx (Ireland)Rambus (United States)Rambus (United Kingdom)Stanford University

About

Yohan Frans is an author at Xilinx (United States) specializing in computer engineering, engineering, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Computer Engineering	23	34	1.4K
2	Engineering	20	29	1K
3	Electrical Engineering	18	23	826
4	Applied Physics	2	2	78
5	Computer Science	1	1	61

Yohan Frans

Publications

1.6K

Citations

H-Index

Page 1

	Year	Citations
A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET Yohan Frans, Jaewook Shin, Lei Zhou, IEEE Journal of Solid-State Circuits Further EqualizationAnalog EqualizationData ConverterMixed-signal Integrated CircuitAnalog Design	2017	155
A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET Jay Im, Kevin Zheng, Chuen-Huei Adam Chou, IEEE Journal of Solid-State Circuits 7-Nm Finfet CmosClock RecoveryData ConverterMixed-signal Integrated CircuitAnalog Design	2020	111
A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET Parag Upadhyaya, Chi Fung Poon, Siok Wei Lim, Low-power ElectronicsHardware SecurityElectrical EngineeringPower ConsumptionEngineering	2018	90
A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling Brian Leibowitz, R. Palmer, John W. Poulton, IEEE Journal of Solid-State Circuits Hardware SecurityLow-power ElectronicsElectrical EngineeringNon-volatile MemoryEngineering	2010	84
6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET Jay Im, Kevin Zheng, Adam Chou, EngineeringVlsi DesignClock RecoveryData CenterMixed-signal Integrated Circuit	2020	83
A 7.4-to-14GHz PLL with 54fs<inf>rms</inf> jitter in 16nm FinFET for integrated RF-data-converter SoCs Didem Turker, Ade Bekele, Parag Upadhyaya, Low-power ElectronicsElectrical EngineeringEngineeringRadio FrequencyAnalog-to-digital Converter	2018	69
A 4-to-16GHz inverter-based injection-locked quadrature clock generator with phase interpolators for multi-standard I/Os in 7nm FinFET Stanley Chen, Lei Zhou, Zhuang Ian,	2018	62
A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface Haechang Lee, Kun-Yung Ken Chang, Jung‐Hoon Chun, IEEE Journal of Solid-State Circuits Link Memory InterfaceElectrical EngineeringEngineeringVlsi DesignMixed-signal Integrated Circuit	2009	61
A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET Jay Im, Freitas Dave, Arianne Roldan, IEEE Journal of Solid-State Circuits Dfe TapElectrical EngineeringEngineeringVlsi DesignMixed-signal Integrated Circuit	2017	59
A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR Brian Leibowitz, Jade Kizer, Haechang Lee, Spectrally Gated AdaptationEngineeringEqualization UpdatesData ConverterMixed-signal Integrated Circuit	2007	53

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