A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET

Abstract

A 40-56 Gb/s PAM-4 receiver with ten-tap decision-feedback equalization (DFE) targeting chip-to-module and board-to-board cable interconnects is designed in 16-nm FinFET. The design implements direct feedback of the first post-cursor (h1) DFE tap to reduce the number of slicers. The h1 feedback signals are directly tapped from the master latch output of the StrongArm-based slicers. A CMOS amplifier with delayed pre-charge release is used to boost and pre-condition the h1 feedback signals before being applied to current-mode logic tap cell for optimum DFE summer settling time. The receiver achieves less than 1E-12 PRBS31 bit error rate (BER) over a channel with 10-dB loss at 14-GHz consuming 230 mW. Fully adapted by off-chip software, the receiver performance demonstrates the effectiveness of direct h1 loop and the need for higher DFE taps to achieve a required BER over channels with reflections. Receiver performance over higher loss channels up to 23 dB and/or under emulated cross-talk noise injection cases are also presented.