Concepedia

3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS

Parag Upadhyaya, Jafar Savoj, Fu-Tai An, Ade Bekele, Anup Jose, Bruce Xu, Daniel Wu, Didem Turker, H.A. Aslanzadeh, Hiva Hedayati,

2015 · 39 citations · 5 references

DOI

Concepts

Abstract

The introduction of high-speed backplane transceivers inside FPGAs has addressed critical issues such as the ease in scalability of performance, high availability, flexible architectures, the use of standards, and rapid time to market. These have been crucial to address the ever-increasing demand for bandwidth in communication and storage systems [1-3], requiring novel techniques in receiver (RX) and clocking circuits.

References

5

CMOS mixers and polyphase filters for large image rejection

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A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology

John F. Bulzacchelli, Christian Menolfi, T. Beukema et al. · IEEE Journal of Solid-State Circuits · 2012 · 175 citations

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A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS

Hiroshi Kimura, Pervez Aziz, Tai Jing et al. · IEEE Journal of Solid-State Circuits · 2014 · 96 citations · Full text

, , +16

2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS

Hiroshi Kimura, Pervez Aziz, Tai Jing et al. · 2014 · 30 citations

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A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology

Gautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli et al. · 2011 · 14 citations

, , +17