2013 · 12 citations · 11 references
EngineeringComputer EngineeringElectrical EngineeringField-programmable Gate ArraysSystem-on-chip DesignVlsi DesignBuilt-in Self-testCmos Circuit DesignDesign For TestabilityFpga ArchitectureLow-power Digital Circuit DesignPower OptimizationFault CoverageField-programmable Gate Arrays (Fpgas)Logic BistLow-power Design For TestabilityOn-chip Test Pattern GenerationSelf-testSoft-core Processor CoresSwitching Activity Reduction
This paper presents a novel test pattern generator which is more suitable for built in self test (BIST) structures used for testing of VLSI circuits. The purpose of the BIST is to reduce power dissipation without affecting the fault coverage. The demonstrated test pattern generator reduces the switching activity among the test patterns at the most. In this method, the single input change patterns generated by a counter and a gray code generator are Exclusive-ORed with the seed generated by the low power linear feedback shift register (LP- LFSR). The proposed scheme is evaluated by using a 4x4 Braun array multiplier. The System-On-Chip (SOC) approach is adopted for implementation on Altera Field Programmable Gate Arrays (FPGAs) based SOC kits with Nios II soft-core processor. From the implementation results, it is verified that the testing power for the proposed method is reduced by a significant percentage.
11
A distributed BIST control scheme for complex VLSI devices
Y. Zorian · 2002 · 543 citations
Engineering, Computer Engineering, Electrical Engineering +12
A modified clock scheme for a low power BIST test pattern generator
Patrick Girard, L. Guiller, C. Landrault et al. · 2002 · 134 citations
Engineering, Computer Engineering, Electrical Engineering +17