Investigation of the impact of the oxide thickness and RESET conditions on disturb in HfO<inf>2</inf>-RRAM integrated in a 65nm CMOS technology

Abstract

In this work, a comprehensive investigation of disturb in HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> -Resistive Random Access Memories (RRAM) integrated in an advanced 65nm technology is presented. The effects of the oxide thickness and RESET conditions on disturb immunity of the High-Resistance-State (HRS) are explored. Constant Voltage Stress is applied on a large amount of samples at various temperatures. Data are collected and analyzed on a statistical basis. The SET dependence to the RESET conditions is investigated and correlated to the length of the induced depleted gap along the conductive filament. The conduction mechanism of the HRS is correlated to the failure/SET process of the RRAM device through a voltage acceleration model. It is shown that thicker dielectric oxide and stronger RESET conditions give rise to longer failure times.