IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2009 · 41 citations · 20 references
Electrical EngineeringCircuit AnalysisEngineeringComputer EngineeringCrosstalk Noise ModelTransmission LineInterconnection NetworkEfficient DelayLie FormulaInterconnection Network ArchitectureComputational ElectromagneticsCrosstalk ModelingCircuit SimulationCoupled Rlc LinesInterconnect (Integrated Circuits)Electromagnetic Compatibility
This paper presents a delay and crosstalk noise model for coupled resistance-inductance-capacitance (RLC) on-chip interconnects. The proposed algorithm, based on a modified Lie formula, is used to convert the solution of the transmission line network into delay algebraic equations to obtain the time domain response. The proposed algorithm is not limited to fixed number of coupled RLC lines or to specific topologies and can be used to model both identical and nonidentical multiconductor lines and loads. For the example presented in this paper, the 50% delay and crosstalk using the proposed method agrees with SPICE results to within 0.75% average error.
20