2004 · 72 citations · 21 references
EngineeringComputer EngineeringElectrical EngineeringDesign OptimizationMicroelectronicsVlsi DesignCmos Circuit DesignIntegrated Circuit DesignLow-power Digital Circuit DesignPower OptimizationPower-aware DesignTiming AnalysisCircuit-level OptimizationDeterministic OptimizationGate Delay ModelingGate SizingGate-level Power OptimizationRobust Linear ModelsRobust Linear ProgrammingStatistical Process Optimization
In this paper, we approach the gate sizing problem in VLSI circuits in the context of increasing variability of process and circuit parameters as technology scales into the nanometer regime. We present a statistical sizing approach that takes into account randomness in gate delays by formulating a robust linear program that can be solved efficiently. We demonstrate the efficiency and computational tractability of the proposed algorithm on the various ISCAS'85 benchmark circuits. Across the benchmarks, compared to the deterministic approach, the power savings range from 23-30% for the same timing target and the yield level, the average power saving being 28%. The runtime is reasonable, ranging from a few seconds to around 10 mins, and grows linearly.
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CMOS scaling into the nanometer regime
Yuan Taur, D. A. Buchanan, Wei Chen et al. · Proceedings of the IEEE · 1997 · 889 citations
Engineering, Computer Engineering, Electrical Engineering +17
An exact solution to the transistor sizing problem for CMOS circuits using convex optimization
Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1993 · 314 citations
Engineering, Computer Engineering, Electrical Engineering +17
Death, taxes and failing chips
Chandu Visweswariah · 2003 · 203 citations