Circuit-level Optimization

Circuit-Level Optimization is a systematic methodology within electronic design automation that specifically targets the minimization of power consumption and delay in digital circuits by adjusting circuit parameters and structures at the transistor and gate level to operate efficiently near the threshold voltage.

630

Publications

26.3K

Citations

1.7K

Authors

431

Institutions

Publications per year

2017–2026

134

Authors

1.7K

  1. KR
    Kaushik Roy

    Purdue University West Lafayette, United States

    10 publications · 1.2K citations

    10

    h-index

  2. AS
    Alberto Sangiovanni‐Vincentelli

    University of California, Berkeley, United States

    9 publications · 959 citations

    9

    h-index

  3. DS
    Dennis Sylvester

    University of Michigan, United States

    9 publications · 326 citations

    9

    h-index

  4. DB
    David Blaauw

    University of Michigan, United States

    8 publications · 794 citations

    8

    h-index

  5. DZ
    David Z. Pan

    The University of Texas at Austin, United States

    5 publications · 156 citations

    7

    h-index

1–5 of 1.7K

Venues

  1. 26

    h-index

  2. 18

    h-index

  3. 12

    h-index

  4. IEEE Journal of Solid-State Circuits

    12 publications · 1.2K citations

    12

    h-index

  5. 11

    h-index

1–5