Access devices for 3D crosspoint memory

TLDR

New nonvolatile memory technologies such as phase change, resistive, and spin‑torque‑transfer magnetic RAM are driven by applications like storage‑class memory, embedded NVM, enhanced SSDs, and neuromorphic computing, requiring densely packed crosspoint arrays that demand strong IV nonlinearity to suppress leakage, achievable either by discrete access devices or highly nonlinear NVM cells. This article reviews progress toward implementing access device functionality, emphasizing the need to stack crosspoint arrays vertically above a silicon wafer to boost effective areal density. The authors outline circuit‑level considerations for crosspoint memory, describe the access device’s role in minimizing leakage while delivering appropriate voltages and currents, list the criteria an access device must meet, survey discrete options ranging from silicon semiconductors to oxide tunnel barriers and mixed‑ionic‑electronic conductors, and discuss self‑selected nonvolatile memories based on resistive RAM.

Abstract

The emergence of new nonvolatile memory (NVM) technologies—such as phase change memory, resistive, and spin-torque-transfer magnetic RAM—has been motivated by exciting applications such as storage class memory, embedded nonvolatile memory, enhanced solid-state disks, and neuromorphic computing. Many of these applications call for such NVM devices to be packed densely in vast “crosspoint” arrays offering many gigabytes if not terabytes of solid-state storage. In such arrays, access to any small subset of the array for accurate reading or low-power writing requires a strong nonlinearity in the IV characteristics, so that the currents passing through the selected devices greatly exceed the residual leakage through the nonselected devices. This nonlinearity can either be included explicitly, by adding a discrete access device at each crosspoint, or implicitly with an NVM device which also exhibits a highly nonlinear IV characteristic. This article reviews progress made toward implementing such access device functionality, focusing on the need to stack such crosspoint arrays vertically above the surface of a silicon wafer for increased effective areal density. The authors start with a brief overview of circuit-level considerations for crosspoint memory arrays, and discuss the role of the access device in minimizing leakage through the many nonselected cells, while delivering the right voltages and currents to the selected cell. The authors then summarize the criteria that an access device must fulfill in order to enable crosspoint memory. The authors review current research on various discrete access device options, ranging from conventional silicon-based semiconductor devices, to oxide semiconductors, threshold switch devices, oxide tunnel barriers, and devices based on mixed-ionic-electronic-conduction. Finally, the authors discuss various approaches for self-selected nonvolatile memories based on Resistive RAM.