International Conference on Computer Aided Design · 1994 · 94 citations · 51 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureComputer NetworksLogicBoolean AlgebraBoolean Network ModelsCombinational Logic DescriptionDigital Logic DesignLogic SynthesisRedundancy TechniquesAutomatic Test Pattern GenerationCombinational Circuit OptimizationCombinational Logic DesignCombinational Logic SynthesisLogic Gate DesignLogic Gate NetworksMulti-level Logic DesignRedundant Logic Design
In this paper, we discuss the problem of optimizing a multi-level logic combinational Boolean network. Our techniques apply a sequence of local perturbations and modifications of the network which are guided by the automatic test pattern generation ATPG based reasoning. In particular, we propose several new ways in which one or more redundant gates or wires can be added to a network. We show how to identify gates which are good candidates for local functionality change. Furthermore, we discuss the problem of adding and removing two wires, none of which alone is redundant, but when jointly added/removed they do not affect functionality of the network. We also address the problem of efficient redundancy computation which allows to eliminate many unnecessary redundancy tests. We have performed experiments on MCNC benchmarks and compared the results to those of misII and RAMBO. Experimental results are very encouraging.
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Sequential circuit design using synthesis and optimization
Ellen Sentovich, K.J. Singh, Cho W. Moon et al. · 2003 · 615 citations
Fast prototyping of datapath-intensive architectures
Jan M. Rabaey, Chi-min Chu, Phu Hoang et al. · IEEE Design & Test of Computers · 1991 · 305 citations