Combinational Circuit Optimization

Combinational Circuit Optimization is a formal methodology within digital logic design that systematically reduces the complexity, area, or delay of a combinational circuit while preserving its logical functionality.

305

Publications

15K

Citations

618

Authors

255

Institutions

Publications per year

2017–2026

Parents

Combinational Logic Description

Publications

305

A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN

F. Brglez · Medical Entomology and Zoology · 1985 · 1.3K citations

Engineering, Computer Engineering, Computer Science +10

DAG-aware AIG rewriting a fresh look at combinational logic synthesis

Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton · 2006 · 484 citations

Engineering, Computer Engineering, Computer Science +17

Test set compaction algorithms for combinational circuits

İlker Hamzaoğlu, J.H. Patel · 1998 · 432 citations · Full text

Engineering, Computer Engineering, Computer Science +14

Techniques for minimizing power dissipation in scan and combinational circuits during test application

V. Dabholkar, S. Chakravarty, Irith Pomeranz et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1998 · 320 citations

Engineering, Computer Engineering, Computer Science +17

An exact solution to the transistor sizing problem for CMOS circuits using convex optimization

Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1993 · 314 citations

Engineering, Computer Engineering, Electrical Engineering +17

1–5 of 305

Authors

618

RK
Robert K. Brayton
University of California, Berkeley, United States
19 publications · 2K citations
16
h-index
AS
Alberto Sangiovanni‐Vincentelli
University of California, Berkeley, United States
10 publications · 1.1K citations
10
h-index
GD
Giovanni De Micheli
École Polytechnique Fédérale de Lausanne, Switzerland
9 publications · 346 citations
9
h-index
SM
Sharad Malik
Princeton University, United States
8 publications · 393 citations
8
h-index
KC
Kwang‐Ting Cheng
University of California, Santa Barbara, United States
6 publications · 546 citations
6
h-index

1–5 of 618

Institutions

255

1–8 of 255

Venues

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
33 publications · 2.7K citations
24
h-index
IEEE Transactions on Computers
23 publications · 844 citations
17
h-index
27th ACM/IEEE Design Automation Conference
Conference · 7 publications · 351 citations
7
h-index
International Conference on Computer Aided Design
Conference · 6 publications · 317 citations
6
h-index
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
5 publications · 163 citations
5
h-index

1–5