CMOS Circuit Speed and Buffer Optimization

TLDR

The authors present an improved timing model for CMOS combinational logic and apply it to optimize output buffers for minimum delay. The model analytically derives the CMOS inverter output response to an input ramp, enabling calculation of propagation delay as the sum of step‑response and input‑dependent components. Compared to the step‑response model, the ramp‑based model captures 50–100 % of the total delay, yields excellent agreement with measured outputs, shows short‑circuit current is negligible, and indicates that optimal buffer tapering factors lie between 3 and 5, with the last stage requiring a larger factor.

Abstract

An improved timing model for CMOS combinational logic is presented. The model is based on an analytical solution for the CMOS inverter output response to an input ramp. This model yields a better understanding of the switching behavior of the CMOS inverter than the step-response model by considering the slope of the input waveform. Essentially, the propagation delay is shown to be the sum of the step-response delay and an input dependent delay that may account for as much as 50-100 percent of the total delay. The matching between the ramp input and the characteristic input waveforms is shown to be easily performed for excellent agreement in output response and propagation delay. Even though the short-circuit current is neglected, its influence is shown to be small and may be corrected. As an example, the timing model is used to optimize CMOS output buffers for minimum delay. If the intrinsic output load capacitance is included in the model, the optimum tapering factor is shown to be not e but a value in the range 3-5 depending on process parameters and design style. Also, due to the input dependence of the propagation delay, the last inverter stage in the buffer should have a larger tapering factor than the other stages for minimum delay.