2005 · 46 citations · 2 references
EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesDevice CharacterizationDevice ModelingDevice ScalingMetal-oxide-semiconductor Field-effect TransistorsMos CapacitorsWide-bandgap Semiconductor DevicesCapacitanceCapacitance ReductionDevice Scaling EffectsGate Leakage CurrentGate Oxide LeakageGate Oxide ScalingLeakage Current ReductionScaling Effects In Cmos
In this paper, the impact of gate underlap on the effective gate capacitance and gate tunneling current in DGMOS devices has been demonstrated. It is shown that in scaled devices, fringing capacitance dominates the effective gate capacitance. Hence with optimum underlap the effective gate capacitance can be reduced thereby reducing the delay and power. Gate underlapping also reduces gate direct tunneling current in the off-state.
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