A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS

Abstract

This paper describes a motion estimation engine fabricated in 65 nm CMOS, targeted for special-purpose on-die acceleration of sum of absolute difference (SAD) computation in real-time video encoding workloads on power-constrained mobile microprocessors. Four-way speculative difference computation using dual 4:2 compressors, optimal reuse of sum XOR min-terms in static 4:2 compressor carry gates, distributed accumulation of input carries for efficient negation and robust ultra-low voltage optimized circuits enable peak SAD efficiency of 12.8 macro-block SADs/nJ within a dense layout occupying 0.089 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> while achieving: (i) scalable performance up to 2.4 GHz, 82 mW measured at 1.4 V, 50degC , (ii) deep subthreshold operation measured at 230 mV while operating down to 4.3 MHz and consuming 14.4 muW , (iii) maximum energy efficiency of 411 GOPS/Watt by operating at 320 mV, 23 MHz and consuming 56 muW (9.6x higher efficiency than nominal 1.2 V operation), (iv) 20% higher energy efficiency for up-conversion of ultra-low voltage signals using a two-stage cascaded split-output level shifter, and (v) tolerance of up to plusmn2x process and temperature induced performance variation using supply voltage compensation of plusmn50 mV.