Publication | Closed Access
An Analysis of Single Event Upset Dependencies on High Frequency and Architectural Implementations within Actel RTAX-S Family Field Programmable Gate Arrays
35
Citations
4
References
2006
Year
EngineeringVlsi DesignEvolvable HardwareElectronic DesignComputer ArchitectureSystem-level DesignHigh FrequencyHigh Speed TestingHardware SystemsHardware SecuritySystems EngineeringHardware-in-the-loop SimulationComputer EngineeringArchitectural EffectsComputer ScienceArchitectural ImplementationsMicroelectronicsFpga DesignDesign For TestingHardware EmulationVlsi ArchitectureRtax-s Fpga Devices
<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> In order to investigate frequency and architectural effects on Single Event Upset cross sections within RTAX-S FPGA devices, a novel approach to high speed testing is implemented. Testing was performed at variable speeds ranging from 15 MHz to 150 MHz. </para>
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