IEEE Transactions on Nuclear Science · 2006 · 35 citations · 4 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureField-programmable Gate ArraysMicroelectronicsBuilt-in Self-testDesign For TestabilityField-programmable Gate Array ArchitectureFpga ArchitectureTiming AnalysisField-programmable Gate Array TestabilityHigh-speed TestingSingle Event Upset ModelingTiming Violation Analysis
<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> In order to investigate frequency and architectural effects on Single Event Upset cross sections within RTAX-S FPGA devices, a novel approach to high speed testing is implemented. Testing was performed at variable speeds ranging from 15 MHz to 150 MHz. </para>
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Paul W. Marshall, Martin A. Carts, A.B. Campbell et al. · IEEE Transactions on Nuclear Science · 2004 · 36 citations
Engineering, Computer Engineering, Electrical Engineering +14
James W. Howard, H. Kim, Melanie D. Berg et al. · NASA Technical Reports Server (NASA) · 2006 · 14 citations
Engineering, Computer Engineering, Electrical Engineering +14