IEEE Transactions on Nuclear Science · 2008 · 151 citations · 59 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignIntegrated Circuit DesignPhysical DesignRadiation HardeningRadiation ResistanceRadiation-resistant MaterialsHardnessRadiation EffectsRadiation Hardening By DesignRadiation HardnessRadiation-hard DevicesRadiation-hard ElectronicsRadiation-hardened Integrated CircuitsRadiation-hardening Techniques
High‑performance, low‑power radiation‑hardened microelectronics enable space system performance, but commercial CMOS foundries require radiation mitigation. The paper aims to describe fabrication approaches for radiation‑hardened components in commercial CMOS foundries using novel design techniques at the transistor, cell, and system levels and to discuss trends in intrinsic radiation hardness. The authors propose a hardness‑by‑design approach that applies novel design techniques at the transistor, cell, and system levels to fabricate radiation‑hardened components in commercial CMOS foundries.
Increased space system performance is enabled by access to high-performance, low-power radiation-hardened microelectronic components. While high performance can be achieved using commercial CMOS foundries, it is necessary to mitigate radiation effects. This paper describes approaches to fabricating radiation-hardened components at commercial CMOS foundries by the application of novel design techniques at the transistor level, the cell level, and at the system level. This approach is referred to as hardness-by-design. In addition, trends in the intrinsic radiation hardness of commercial CMOS processes will be discussed.
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