Test time reduction in scan designed circuits

Abstract

The reduction of test application time for the general scan designed circuits has been studied. The reduction problem is investigated from three aspects: the test generation, selective scans, and rearrangement of scan path. The two phase testing strategy has been proposed to employ scan only for the hard-to-detect faults. Four cases of selective scan have also been identified. Furthermore, an ordering heuristic without layout constraint has been proposed to maximize the reduction of unnecessary scans and hence the test application time. Applying these reduction methods, the total test clock-cycles can be reduced to only 20% on average for ISCAS sequential benchmark circuits with partial scan.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>