Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections

TLDR

A 3‑D integration technology was developed to fabricate a new 3‑D shared‑memory test chip. The method uses wafer bonding and thinning, creating 2‑µm‑diameter, 50‑µm‑deep trenches filled with n+ polycrystalline silicon or tungsten to form vertical buried interconnections, along with metal microbump formation, stacked wafer thinning, wafer alignment, and bonding to assemble three‑layer shared‑memory test chips. The fabricated 3‑D devices showed no characteristic degradation, and fundamental memory and inter‑layer broadcast operations functioned successfully across the three layers.

Abstract

A three-dimensional (3-D) integration technology has been developed for the fabrication of a new 3-D shared-memory test chip. This 3-D technology is based on the wafer bonding and thinning method. Five key technologies for 3-D integration were developed, namely, the formation of vertical buried interconnections, metal microbump formations, stacked wafer thinning, wafer alignment, and wafer bonding. Deep trenches having a diameter of 2 mum and a depth of approximately 50 mum were formed in the silicon substrate using inductively coupled plasma etching to form vertical buried interconnections. These trenches were oxidized and filled with n+ polycrystalline silicon or tungsten. The 3-D devices and 3-D shared-memory test chips with three-stacked layers were fabricated by bonding the wafers with vertical buried interconnections after thinning. No characteristic degradation was observed in the fabricated 3-D devices. It was confirmed that fundamental memory operation and broadcast operation between the three memory layers could be successfully performed in the fabricated 3-D shared-memory test chip