2000 · 47 citations · 10 references
EngineeringComputer EngineeringComputer ScienceAlgorithmsDesign OptimizationMicroelectronicsIntegrated Circuit DesignTiming AnalysisArea OptimizationCircuit OptimizationCombinational Cell DesignCombinational Circuit OptimizationGate SizingNegative SlackPlacement AlgorithmsTiming-driven Placement
This paper proposes the concept of potential slack and show it is an effective metric of combinational circuit performance. We provide several methods for estimating potential slack and prove one (a maximal-independent-set based algorithm) in particular works best. Experiments in gate sizing show that potential slack provides 100% correct prediction for circuit area optimization. We also explore the role of potential slack in timing-driven placement.
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SIS : A System for Sequential Circuit Synthesis
Ellen Sentovich · 1992 · 1.9K citations
Timing driven placement for large standard cell circuits
W. H. Swartz, Carl Sechen · 1995 · 172 citations · Full text
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