Generation of performance constraints for layout

Abstract

Methods are presented for generating bounds on interconnection delays in a combinational network having specified timing requirements at its input and output terminals. An automatic placement program that uses wirability as its primary objective could use these delay bounds to generate length or capacitance bounds for interconnection nets as secondary objectives. Thus, unlike previous timing-driven placement algorithms, the desired performance of the circuit is guaranteed when a wirable placement meeting these objectives is found. Fast algorithms are provided that maximize the delay range, and hence the margin for error in layout, for various types of timing constraint.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>